With Roman's new firmware on aifoundry3's card, my agents heated chosen parts of the die in on/off cycles and read all 35 temperature sensors twenty times a second. Blocks of four or more shires light up their corner of the die and the heat visibly spreads; one core, or one shire of 32 cores, never moves its own sensor by a whole degree. The movies below average every repeat of a cycle, which is what pulls sub-degree changes out of whole-degree readings. The sensor map was measured first, and the movies use it.
35temperature sensors read, every 50 ms
83heating cycles, 8 s on and 12 s off
0.58fit of separate runs with the measured sensor map, against 0.41 with the latency map
1 °Cstep of each reading; a shire's own rise is about 0.5 °C
Watch it: one heating cycle, averaged over every repeat
−0.5 °C+0.5 °C
Outlined cells are the heated shires. The red band is the heater; time 0 is the start of the heater's process. Cells follow the lab's die map from on-chip latency. With "measured sensor map" on, each sensor sits where the sensor-map runs below placed it; off, sensor n sits at shire n.
Blocks of shires show; one core or one shire does not
Every block run raised its own region above the rest of the die, by up to +1.26 °C (the east half (14 shires)). The single core and the three single shires never moved their own sensor: in every cycle it stayed on the same whole degree. A shire's expected rise is about half a degree, and whole degrees can't show that without a dither the idle card doesn't provide. For single shires it is not granular enough: that needs the raw 12-bit codes, 0.061 °C a step, which Roman is adding to the firmware.
Run
Cycles
Heated, peak
Whole die, peak
Heated minus rest
Sensors that moved
Seen?
One core (1 of 32) in shire S14, the centre
3
+0.00
+0.03
+0.03
6 / 34
No: one core draws about 20 mW
One shire, S0: the NW corner
4
+0.00
+0.14
-0.00
12 / 34
No: under one whole degree
One shire, S31: the SE corner
4
+0.00
+0.10
+0.01
7 / 34
No: under one whole degree
One shire, S14: the centre
4
+0.00
+0.17
-0.00
12 / 34
No: under one whole degree
A 2×2 block in the centre (S13, S14, S21, S22)
4
+1.20
+0.74
+0.52
34 / 34
Yes
The NW quadrant (9 shires)
5
+2.00
+1.55
+0.64
34 / 34
Yes
The NE quadrant (6 shires)
5
+1.49
+0.86
+0.80
32 / 34
Yes
The SW quadrant (9 shires)
5
+1.92
+1.40
+0.88
34 / 34
Yes
The SE quadrant (8 shires)
5
+1.88
+1.11
+1.14
34 / 34
Yes
The west half (18 shires)
4
+3.29
+3.07
+0.67
34 / 34
Yes
The east half (14 shires)
4
+2.68
+2.00
+1.26
34 / 34
Yes
Where each sensor sits: the latency map is broadly right, and the measured map is better
To place the sensors, my agents heated every column of the die in turn, then every row, then two corners, and compared each sensor's responses with a heat-spread model (0.52 °C at the source, 0.24 °C one tile away, 0.10 °C two away). The assumed layout, sensor n at shire n's place on the latency map, fits these 14 patterns far better than chance (total correlation 13.7, against 0.0 for random relabelings), so heat sources and sensors broadly line up. It is not exact: only 15 of 35 sensors have their assumed cell among their three best fits. Sensors 13 and 14 are the clearest: they stay cold when the west half, with shires 13 and 14, heats, and warm with the east half.
The best placement fitted on these patterns alone was then checked on the main session's eight separate runs: it explains them better than the assumed layout (correlation 0.58 against 0.41 on average; 0.78 against 0.42 for the west half). The movies use it. Any single sensor's place is approximate, since whole degrees and three cycles a stripe leave room; raw codes would settle it.
S0+0.13
S8+0.56
S3+0.12
M32-0.35
I/O-0.74
PCIe
S24+0.15
S16-0.01
S4-0.36
S12+0.26
S20-0.25
S28+0.25
S9+0.77
S1+0.10
S13-0.13
S21+0.15
S29-0.38
S5-0.74
S25+0.02
S17+0.10
S14-0.65
S22-0.30
S30-0.51
S6-0.33
S2+0.87
S10+0.23
S18+0.25
S26+0.06
S15-0.44
S7-0.07
S11+0.55
S19+0.90
S27+0.14
M33-0.62
S23-0.72
S31+0.26
column 1 heated
S0-0.52
S8+0.17
S3+0.75
M32+0.59
I/O-0.13
PCIe
S24+0.14
S16+0.10
S4+0.14
S12+0.01
S20+0.14
S28-0.05
S9+0.06
S1-0.39
S13-0.85
S21+0.09
S29+0.14
S5-0.81
S25+0.47
S17+0.60
S14-0.85
S22+0.14
S30-0.13
S6+0.14
S2+0.09
S10-0.62
S18+0.35
S26+0.51
S15-0.86
S7+0.13
S11+0.12
S19+0.08
S27+0.20
M33-0.21
S23+0.11
S31+0.01
column 2 heated
S0+0.17
S8-0.19
S3+0.14
M32+0.09
I/O-0.02
PCIe
S24+0.46
S16+0.04
S4+0.07
S12-0.03
S20-0.16
S28+0.37
S9-0.51
S1+0.18
S13-0.45
S21-0.22
S29+0.21
S5+0.15
S25+0.05
S17+0.18
S14-0.02
S22+0.06
S30+0.62
S6-0.24
S2-0.69
S10-0.06
S18+0.21
S26+0.05
S15-0.38
S7-0.20
S11-0.76
S19-0.54
S27+0.55
M33+0.45
S23+0.13
S31+0.30
column 3 heated
S0-0.51
S8+0.19
S3+0.04
M32+0.16
I/O-0.39
PCIe
S24-0.51
S16+0.09
S4+0.16
S12-0.03
S20+0.32
S28+0.30
S9-0.20
S1-0.41
S13+0.26
S21+0.47
S29+0.28
S5-0.48
S25+0.44
S17-0.22
S14-0.26
S22+0.59
S30+0.32
S6+0.21
S2-0.18
S10-0.51
S18-0.51
S26+0.45
S15-0.20
S7+0.52
S11-0.16
S19+0.06
S27-0.51
M33-0.44
S23-0.08
S31+0.34
column 4 heated
S0-0.54
S8-0.45
S3+0.38
M32+0.38
I/O+0.21
PCIe
S24-0.41
S16+0.37
S4+0.38
S12-0.62
S20+0.38
S28-0.62
S9-0.62
S1+0.37
S13+0.17
S21+0.29
S29+0.38
S5+0.07
S25-0.29
S17+0.38
S14+0.12
S22+0.38
S30+0.38
S6+0.65
S2-0.62
S10-0.62
S18+0.16
S26-0.16
S15+0.14
S7+0.35
S11-0.62
S19-0.62
S27-0.15
M33+0.34
S23+0.38
S31-0.04
column 5 heated
S0-0.09
S8-0.54
S3+0.35
M32+0.10
I/O+0.46
PCIe
S24+0.13
S16-0.32
S4+0.16
S12-0.54
S20+0.41
S28-0.54
S9-0.54
S1+0.44
S13+0.22
S21+0.26
S29+0.40
S5-0.41
S25-0.54
S17+0.46
S14+0.18
S22+0.45
S30+0.46
S6+0.46
S2-0.54
S10-0.42
S18+0.43
S26-0.54
S15+0.20
S7+0.36
S11-0.54
S19-0.54
S27+0.23
M33+0.46
S23+0.46
S31-0.54
column 6 heated
S0+0.63
S8+0.42
S3-0.33
M32-0.33
I/O-0.04
PCIe
S24+0.66
S16+0.70
S4+0.44
S12+0.38
S20-0.33
S28-0.14
S9-0.32
S1+0.64
S13-0.25
S21-0.33
S29-0.33
S5+0.46
S25-0.33
S17+0.58
S14+0.05
S22-0.33
S30-0.14
S6-0.33
S2-0.33
S10+0.29
S18+0.42
S26-0.33
S15+0.03
S7-0.33
S11-0.33
S19-0.33
S27+0.23
M33-0.28
S23-0.33
S31-0.22
row 0 heated
S0+0.18
S8+0.15
S3+0.05
M32-0.61
I/O+0.18
PCIe
S24+0.88
S16+0.18
S4+0.18
S12+0.10
S20+0.31
S28+0.30
S9-0.27
S1+0.18
S13+0.25
S21+0.05
S29+0.15
S5+0.87
S25+0.07
S17+0.18
S14+0.12
S22+0.11
S30+0.18
S6+0.06
S2-0.77
S10+0.18
S18+0.18
S26-0.23
S15-0.29
S7-0.78
S11-0.82
S19-0.82
S27+0.18
M33+0.16
S23-0.13
S31-0.49
row 1 heated
S0-0.55
S8+0.15
S3+0.15
M32+0.15
I/O+0.15
PCIe
S24-0.36
S16+0.15
S4+0.15
S12+0.05
S20+0.15
S28+0.02
S9+0.01
S1+0.13
S13+0.01
S21+0.25
S29+0.84
S5-0.70
S25+0.39
S17+0.84
S14-0.83
S22+0.15
S30+0.72
S6+0.15
S2+0.04
S10-0.80
S18+0.34
S26+0.15
S15-0.85
S7+0.15
S11-0.66
S19-0.32
S27-0.36
M33+0.13
S23+0.15
S31-0.04
row 2 heated
S0-0.89
S8+0.11
S3+0.41
M32+0.11
I/O-0.69
PCIe
S24-0.89
S16+0.10
S4+0.11
S12-0.01
S20+0.11
S28+0.01
S9+0.09
S1-0.85
S13+0.07
S21+0.11
S29+0.11
S5-0.89
S25+0.11
S17-0.44
S14-0.08
S22+0.81
S30+0.79
S6+0.79
S2+0.11
S10-0.17
S18-0.17
S26+0.79
S15+0.03
S7+0.11
S11+0.11
S19+0.11
S27-0.12
M33-0.77
S23+0.08
S31+0.10
row 3 heated
S0-0.81
S8+0.19
S3+0.86
M32+0.72
I/O-0.81
PCIe
S24-0.81
S16+0.19
S4+0.19
S12-0.81
S20+0.19
S28-0.81
S9-0.02
S1-0.81
S13-0.04
S21+0.19
S29+0.19
S5-0.81
S25+0.19
S17-0.59
S14+0.01
S22+0.19
S30+0.14
S6+0.19
S2+0.19
S10-0.05
S18-0.81
S26+0.19
S15+0.16
S7+0.88
S11+0.19
S19+0.19
S27-0.03
M33-0.05
S23+0.75
S31+0.50
row 4 heated
S0-0.51
S8-0.22
S3+0.45
M32+1.18
I/O-0.05
PCIe
S24-0.51
S16+0.37
S4-0.10
S12-0.51
S20-0.23
S28-0.51
S9-0.51
S1-0.09
S13-0.51
S21-0.45
S29+0.49
S5-0.51
S25-0.34
S17+0.18
S14-0.49
S22+0.49
S30+0.29
S6+0.49
S2-0.42
S10-0.51
S18-0.40
S26+0.38
S15+0.27
S7+0.47
S11+0.44
S19+0.47
S27-0.50
M33+0.61
S23+0.44
S31+0.31
row 5 heated
Each small map is the die at the end of heating, minus the whole-die rise, drawn on the latency map: red where a sensor rose more than average. Outlined: the heated shires.
The measured placement
S0✓
S17from r3c2
S1from r2c2
S16from r1c2
S4from r1c3
PCIe
S8from r0c2
S241 cell
S121 cell
S5from r2c6
S13from r2c3
I/Ofrom r0c5
S9✓
S18from r4c3
S28from r1c6
S291 cell
S211 cell
S20from r1c5
S21 cell
S251 cell
S26from r4c4
S301 cell
S221 cell
S6✓
S101 cell
S3from r0c3
S271 cell
S7from r4c6
S231 cell
S14from r3c3
S191 cell
S111 cell
S31from r5c6
M32from r0c4
S151 cell
M33from r5c4
✓: the sensor sits where the latency map put it. Dashed: one cell away. Amber: further; the cell says where the latency map had it.
Every run at its sharpest moment
S0-0.17
S17+0.00
S1-0.33
S16+0.00
S4+0.00
PCIe
S8+0.00
S24-0.38
S12+0.00
S5+0.00
S13+0.00
I/O-0.06
S9+0.00
S18-0.14
S28+0.00
S29+0.00
S21+0.00
S20+0.00
S2+0.00
S25+0.00
S26+0.00
S30+0.00
S22+0.00
S6+0.00
S10+0.00
S3+0.00
S27+0.07
S7+0.00
S23+0.00
S14+0.00
S19+0.00
S11+0.00
S31+0.00
M32+0.00
S15+0.00
M33+0.00
One core (1 of 32) in shire S14, the centre 3 cycles · at +8.75 s · heated +0.00 °C, rest of die -0.03 °C
S0+0.00
S17+0.02
S1+0.01
S16+0.00
S4+0.00
PCIe
S8+0.00
S24+0.04
S12+0.00
S5+0.00
S13+0.00
I/O+0.00
S9+0.00
S18-0.07
S28+0.00
S29+0.00
S21+0.00
S20+0.00
S2+0.00
S25+0.00
S26+0.00
S30+0.00
S22+0.00
S6+0.00
S10+0.00
S3+0.00
S27+0.12
S7+0.00
S23+0.00
S14+0.00
S19+0.00
S11+0.00
S31+0.00
M32+0.00
S15+0.00
M33-0.13
One shire, S0: the NW corner 4 cycles · at +0.00 s · heated +0.00 °C, rest of die +0.00 °C
S0+0.00
S17-0.14
S1+0.00
S16-0.04
S4+0.00
PCIe
S8+0.00
S24+0.00
S12+0.00
S5+0.00
S13+0.00
I/O+0.00
S9+0.00
S18+0.00
S28+0.00
S29+0.00
S21+0.00
S20+0.00
S2+0.00
S25+0.00
S26+0.00
S30-0.02
S22+0.00
S6+0.00
S10+0.00
S3-0.01
S27+0.00
S7+0.00
S23+0.00
S14+0.00
S19+0.00
S11+0.00
S31+0.00
M32+0.00
S15+0.00
M33+0.02
One shire, S31: the SE corner 4 cycles · at +0.25 s · heated +0.00 °C, rest of die -0.01 °C
S0+0.00
S17+0.00
S1+0.00
S16+0.03
S4+0.00
PCIe
S8+0.00
S24+0.00
S12+0.00
S5+0.00
S13+0.00
I/O+0.00
S9+0.00
S18+0.00
S28+0.00
S29+0.00
S21+0.00
S20+0.00
S2+0.00
S25+0.00
S26+0.00
S30+0.06
S22+0.00
S6+0.00
S10+0.00
S3-0.06
S27+0.00
S7+0.00
S23+0.02
S14+0.00
S19+0.00
S11+0.00
S31+0.00
M32-0.01
S15+0.00
M33+0.00
One shire, S14: the centre 4 cycles · at +0.00 s · heated +0.00 °C, rest of die +0.00 °C
S0+0.30
S17+0.50
S1+0.25
S16+0.01
S4+0.25
PCIe
S8+0.26
S24+0.80
S12+0.75
S5+0.75
S13+1.00
I/O+0.25
S9+0.75
S18+0.75
S28+1.00
S29+1.27
S21+1.49
S20+0.31
S2+0.71
S25+1.12
S26+1.33
S30+1.01
S22+1.31
S6+0.44
S10+0.70
S3+0.16
S27+1.00
S7+0.81
S23+0.25
S14+0.95
S19+0.64
S11+0.52
S31+1.00
M32+0.24
S15+1.00
M33+0.55
A 2×2 block in the centre (S13, S14, S21, S22) 4 cycles · at +7.25 s · heated +1.19 °C, rest of die +0.67 °C
S0+1.92
S17+2.35
S1+2.00
S16+2.38
S4+1.80
PCIe
S8+2.60
S24+2.60
S12+2.32
S5+1.00
S13+0.97
I/O+0.80
S9+1.85
S18+1.60
S28+2.04
S29+1.93
S21+1.20
S20+1.17
S2+1.40
S25+2.50
S26+1.54
S30+1.32
S22+0.94
S6+0.76
S10+1.00
S3+1.12
S27+1.00
S7+0.75
S23+0.60
S14+0.80
S19+0.80
S11+0.74
S31+0.99
M32+0.73
S15+0.62
M33+0.69
The NW quadrant (9 shires) 5 cycles · at +6.25 s · heated +1.92 °C, rest of die +1.28 °C
S0+0.00
S17+0.74
S1+0.39
S16+1.00
S4+1.00
PCIe
S8+1.00
S24+0.01
S12+1.00
S5+1.00
S13+2.00
I/O+1.48
S9+0.00
S18+0.17
S28+1.00
S29+1.68
S21+2.00
S20+2.00
S2+0.00
S25+1.00
S26+1.00
S30+1.10
S22+1.20
S6+1.68
S10+0.00
S3+1.00
S27+0.04
S7+1.00
S23+1.00
S14+0.48
S19+0.00
S11+0.00
S31+0.96
M32+1.00
S15+0.12
M33+0.55
The NE quadrant (6 shires) 5 cycles · at +7.00 s · heated +1.45 °C, rest of die +0.65 °C
S0+0.00
S17+1.01
S1+0.40
S16+0.18
S4+0.39
PCIe
S8+0.60
S24+0.76
S12+1.00
S5+0.00
S13+0.96
I/O+0.00
S9+1.00
S18+2.00
S28+1.00
S29+0.85
S21+1.00
S20+0.79
S2+1.96
S25+1.32
S26+2.00
S30+1.15
S22+0.78
S6+0.63
S10+1.96
S3+2.19
S27+2.00
S7+1.11
S23+1.15
S14+0.84
S19+3.00
S11+2.00
S31+2.00
M32+2.37
S15+1.00
M33+1.80
The SW quadrant (9 shires) 5 cycles · at +5.25 s · heated +1.79 °C, rest of die +0.91 °C
S0+0.28
S17+0.79
S1+0.44
S16+0.39
S4+0.40
PCIe
S8+0.08
S24+0.42
S12+0.00
S5+0.27
S13+0.80
I/O+0.60
S9+0.00
S18+0.55
S28+0.00
S29+1.00
S21+1.00
S20+0.84
S2+0.00
S25+0.40
S26+0.76
S30+1.33
S22+2.00
S6+2.00
S10+0.27
S3+0.98
S27+0.50
S7+2.00
S23+1.93
S14+2.20
S19+0.24
S11+0.00
S31+1.00
M32+1.00
S15+2.02
M33+1.08
The SE quadrant (8 shires) 5 cycles · at +3.25 s · heated +1.63 °C, rest of die +0.49 °C
S0+2.50
S17+3.50
S1+2.80
S16+3.11
S4+2.65
PCIe
S8+3.50
S24+3.50
S12+3.09
S5+1.50
S13+1.74
I/O+1.00
S9+2.97
S18+3.80
S28+2.76
S29+3.15
S21+2.01
S20+2.00
S2+2.98
S25+3.75
S26+3.70
S30+3.01
S22+2.25
S6+1.75
S10+3.00
S3+3.72
S27+3.50
S7+2.00
S23+1.68
S14+1.75
S19+3.43
S11+2.50
S31+2.97
M32+3.50
S15+1.29
M33+2.60
The west half (18 shires) 4 cycles · at +6.25 s · heated +3.04 °C, rest of die +2.37 °C
S0+0.41
S17+1.60
S1+0.81
S16+1.14
S4+2.00
PCIe
S8+1.20
S24+1.17
S12+1.00
S5+2.34
S13+3.00
I/O+2.55
S9+1.00
S18+1.35
S28+2.00
S29+2.98
S21+3.00
S20+2.99
S2+1.00
S25+2.00
S26+2.00
S30+2.52
S22+3.64
S6+3.90
S10+1.01
S3+1.64
S27+1.21
S7+3.15
S23+2.73
S14+3.01
S19+1.00
S11+1.00
S31+2.25
M32+1.99
S15+3.00
M33+2.17
The east half (14 shires) 4 cycles · at +7.75 s · heated +2.68 °C, rest of die +1.42 °C
No hidden way to finer readings: it takes a firmware change
The sensors resolve 0.061 °C in hardware, but every route from the host gets whole degrees or nothing. Checked on Roman's build on aifoundry3 and in the firmware and driver source:
Route
What it gives
Why
Command 74, temperature group (Roman's build)
Whole degrees
The firmware converts each 12-bit code with integer arithmetic and divides by 1000 before it answers (pvt_controller.c:567-585).
Command 74, other groups
Errors (−9007, no data)
Roman's patch defines groups 0-6; none returns raw temperature codes.
Process detectors (ring oscillators)
A constant (47620), not counts
Their counts would track temperature, but the firmware builds them with measurement disabled (PVT_PD_OSC_SELECT).
The other temperature commands (21, 22, 27, 28, 38)
Whole degrees
Means, peaks, thresholds and throttle state, all in whole °C.
The SP's debug trace
Nothing per sensor
The per-shire temperature print exists, but nothing calls it (pvt_print_all has no caller).
Debug-interface memory reads (MDI)
Not reachable
Allowed only in host-managed DRAM and minion stack regions; the sensor registers are the SP's own.
The PCIe windows the driver maps
Not reachable
Queues, scratch, traces and the SP and MM statistics; the sensor controllers (R_SP_PVT*) are SP-only.
Python and other host software
Nothing
No Python package for the cards on the box; libDM and /opt/et hold no other path; et-pvt-top uses command 74.
What would fix it: return the raw 12-bit code from the same register read that command 74 already makes, with no rounding. Roman has agreed to add it. Until then, averaging repeated cycles is the only way under a degree, and it only works for patterns large enough to cross a degree boundary.
How the runs were made
Card: aifoundry3 card 0, firmware release 1.4.0 (BL1/BL2 0.22.0, minions 0.25.1), Roman's build with command 74. Idle at about 57 °C; the governor is pinned at 600 MHz on this card.
Readings: DM_CMD_GET_ASIC_PVT_SAMPLES group 0 (34 minion-shire sensors) every 50 ms and group 4 (the I/O shire) once a second, sent from Python straight to the management node (42 µs on the card per call). 34138 samples in all, no read errors.
Heat: the lab's fp32 FMA heater (sparsity_host --test fma) on the chosen shires, 32 cores each (one core for the single-core run), 8 s on, 12 s off, 3 to 6 cycles per run, under the card's lock. The hottest reading anywhere was 66 °C.
Movies: every cycle aligned on the heater start, each sensor minus its own mean over the 2 s before, averaged over the cycles in 0.25 s frames.
Layout: the die frame from the lab's latency map (tools/claims-v3/hp/placements.json), with the sensors placed by the measured map above.